1. Field of the Invention
This invention relates to semiconductor fabrication processes, and more particularly, to a method for forming a self-aligned contact (SAC) in a semiconductor device, such as a metal-oxide semiconductor (MOS) device. This method features that it can allow an increase in the area of the resultant self-aligned contact.
2. Description of Related Art
A MOS device is composed of metallization layers, silicon dioxide layers, and substrate. Due to the fact that the adhesion of metal to silicon dioxide is poor, polysilicon is usually used instead of metal to form conductive layers in the gate structure of the MOS device. Although polysilicon-based conductive layers can be doped with impurities to decrease the resistivity thereof, the resultant conductivity is still not adequate enough to serve as good conductive layers in the MOS device. A solution to this problem is to add a layer of metal silicide, such as a layer of tungsten silicide, over the polysilicon layer, whereby the electrical conductivity of the gate structure can be improved.
The method for fabricating a MOS device includes the steps of forming dielectric layers, contact windows, and metallization layers. In the forming of metal contacts between metallization layers and substrate, the self-aligned etching method is the most widely used method. A conventional method for forming a self-aligned contact is illustrated and described in the following with reference to FIGS. 1A through 1C.
Referring to FIG. 1A, in the first step, a substrate 10 is prepared. Subsequently, a plurality of separate gate structures are formed over the substrate 10, each gate structure including a polysilicon layer 11, a layer of tungsten silicide (WSi.sub.2) 12, a layer of silicon nitride 13, and a sidewall spacer 14. After the gate structures are formed, a dielectric layer (inter layer dielectrics) 15 is formed over the entire top surface of the wafer, covering all of the exposed surfaces of the gate structures and the substrate 10.
Referring next to FIG. 1B, in the subsequent step, a photolithographic and etching process is performed on the dielectric layer 15 so as to remove a selected portion of the dielectric layer 15 between the gate structures until the top surface of the substrate 10 is exposed. The etching is also effective on the silicon nitride layer 13 but with a slower etching rate, so that the silicon nitride layer 13 and the sidewall spacer 14 will be partly etched away. As a result of this process, an empty space (referred to as a contact window) 16 is formed between the gate structures, which can be self-aligned to the location on the substrate 10 where a contact area is to be formed. As shown, the contact area is to be formed at the exposed surface of the substrate 10 which has a width indicated by X.
Referring further to FIG. 1C, in the subsequent step, a metallization layer 17 is deposited over the entire top surface of the wafer to a specific thickness, covering all of the exposed surfaces of the dielectric layer 15, the sidewall spacers 14 of the gate structures, and the substrate 10. A metal contact having a width X is thus formed between the metallization layer 17 and the substrate 10 in the self-aligned contact window 16.
The RC (resistance-capacitance) value of the foregoing self-aligned contact is proportional to its contact area (i.e., the area indicated by the width X) between the metallization layer 17 and the substrate 10. One method to increase the contact area is to extend the process time of the etching. However, this will also cause the silicon nitride layer 13 to be further etched away, which can, if the process time is not properly controlled, expose the underlying tungsten silicide layer 12. The exposed part of the tungsten silicide layer 12 will then come into contact with the subsequently formed metallization layer 17, resulting in a short-circuit therebetween. The resultant MOS device is therefore a defect one which should be discarded.